CPU Internals

X86 Register usage and Calling conventions

"I see" Facts: ARM

Name stands for?

 

ARM- Advanced RISC Machines

ARMv7A - 'A' for Applications (NEON, MMU, TrustZone(safe) and Jazelle-RCT(extensible))

ARMv7R - 'R' for Real Time (MPU, Low Latency(How?))

ARMv7M - 'M' for Microcontroller (Deterministic, Deeply embedded, Lowest gate count)

ARM7TDMI - 'T' for Thumb

 

1) Why FIQ is as last vector of ARM vector table?

 

Vector table should have branch instructions to the correpsonding handler. By, keeping the FIQ as last one, it can avoid the branch instruction by keeping the handler just next to the FIQ vector.

 

2) Why FIQ? How is it different from IRQ by hardware architecture?

 

You know, FIQ banks the registers R8～R14 and CPSR (totally 8 registers) to save time required for saving these registers and thus lowering the latency. But, IRQ saves only 3 registers R13, R14, CPSR. And as above, the branch instruction also can be avoided.

 

3) Is return address same when returning from IRQ and data abort?

 

No. For function calls, it can return to the exact LR register address. But, for exceptions, depending on the type of exception, it may be necessary to modify the contents of the link register to get the correct return address. Usually, PC points to the executing instruction, and link register PC+4.

 

Exception occurs when executing an instruction. In the case of an IRQ or FIQ interrupt, the processor will finish its current instruction, increment the PC to the next instruction and then jumping to the vector table. This means that the value in the link register is PC+4 or one instruction ahead of the return address. This means we need to subtract 4 from the value in the link register to get the correct return address. This can be done in a single instruction thus:

 

SUBS pc, r14, #4 // PC = Link register - 4

 

For data abort, the problematic instruction needs to be executed again. So, the return address is LR - 8.

 

+-----------+---------------+------------------------+-----------------------+
| Exception | PC updated to | Return has to be done  | Offset to LR that has |
|                  | next instr?   | to same or next instr? | to be loaded in PC    |
+-----------+---------------+------------------------+-----------------------+
| SWI       | No            | Next                   | PC ← LR              |
| Undefined | No            | Next                   | PC ← LR              |
+-----------+---------------+------------------------+-----------------------+
| IRQ       | Yes           | Next                   | PC ← LR - 4          |
| FIQ       | Yes           | Next                   | PC ← LR - 4          |
+-----------+---------------+------------------------+-----------------------+
| Prefetch  | No            | Same                   | PC ← LR - 4          |
+-----------+---------------+------------------------+-----------------------+
| Data abort| Yes           | Same                   | PC ← LR - 8          |
+-----------+---------------+------------------------+-----------------------+

Program counter points to the instruction on execution. LR points to the next instruction PC+4.

 

When exception occurs, if PC halts in the same instruction, then LR is perfect to return. (The SWI and Undefined Instruction exceptions are generated by the instruction itself, so the PC is not updated when the exception is taken. Therefore storing (PC – 4) in LR_ makes LR_ point to the next instruction to be executed. Restoring the PC from the LR with MOVS pc, lr returns control from the handler.)

 

If PC advances to the next instruction, return should be LR - 4 (Same pointed by PC). For IRQ and FIQ, PC advances to next instruction.

  

Prefetch means instruction fetch itself failed. So, PC halts in the same instruction. But, the instruction at PC has to be exuecuted once again. So, LR - 4. (If the CPU attempts to fetch an instruction from an illegal address the instruction is flagged as invalid. Instructions already in the pipeline continue to execute until the invalid instruction is reached, at which point a prefetch abort is generated. The handler gets the MMU to load the appropriate virtual memory locations into physical memory. Having done this, it must return to the offending address and reload the instruction, which should now load and execute correctly. Because the PC will not have been updated at the time the prefetch abort was issued, LR_ABORT will point to the instruction following the one that caused the exception. The handler must therefore return to LR_ABORT – 4 using:
SUBS pc, lr, #4)

 

For data abort, the PC advances to the next instruction. But, after the MMU loads, the instructions previous to the PC has to be executed. So, PC - 4 == LR - 8. (When a load or store instruction tries to access memory, the PC has been updated. A stored value of (PC – 4) in LR_ABORT points to the second instruction beyond the address where the exception was generated. Once the MMU has loaded the appropriate address into physical memory, the handler should return to the original, aborted instruction so that a second attempt can be made to execute it. The return address is therefore two words (or eight bytes) less than that in LR_ABORT, making the return instruction:
SUBS pc, lr, #8)

 

http://www.imit.kth.se/courses/2B1445/0304/material/Apps25vE.pdf

http://www.iti.uni-stuttgart.de/~radetzki/Seminar06/08_report.pdf

 

Real Time Trace

Real Time Trace is the advanced debug technique where the On-chip debug circuit captures all the events in real time till a particular trigger point which is set by user. So, user can trace back the problem from the trigger point as if a police department trace back the crime site. For example, ARM has Embedded Trace Macrocell (ETM).