STM32F4: Exception occurs when enabling prefetch queue and branch caches

Problem:

On STM32F407IG, when I enable/set Prefetch queue (PRFTEN bit) and branch cache (DCEN and ICEN bits) in Flash access control register (FLASH_ACR) and I execute my program, exception occurs. The exception differs each time between Hard Fault, Bus Fault, and Usage Fault exceptions. If I enable only either Prefetch queue or branch cache, there is no such problem.

Or, when I execute my program through single-step using debugger, there is no exception occurs. But, when I 'Run' from reset-handler, either HardFault or BusFault or UsageFault occurs.

Solution:

Check the LATENCY bit setting. If it has been set to Three wait states (0x3), try to increase it to Four wait states (0x4) or more.

The clock speed has been increased to 168 MHz in STM32F4, in comparison with 120 MHz clock speed in STM32F2. So, the number of wait states has to be increased, if you port a program from STM32F2 to STM32F4 family MCUs.

When the cache is enabled, "Cache Fill" reads more faster from Flash memory. So, if the number of wait states is not more enough, the read data or instruction will be inconsistent. Same phenomenon occurs, when 'Run'ning a program using debugger instead of single-step execution. 'When 'Run'ning a program, memory will be read more faster. So, make sure that enough wait states has been introduced.

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