Caches

1) What are caches?
2) How caches are used in Hardward and Van Neuman architectures to reduce the bottleneck?
3) What are levels of cache?
4) What is fully associative, set associative and not-associative cahces?
5) How is Cache organized and data is stored and retrieved?
6) What is Virtually Indexed and Physically tagged? What is physically indexed and physically tagged?
6) Cache related terms: Cache-hit, Cache-miss, Flush, Invalidate, Cache coherency and Cache snooping, Write-through, Write-back, Dirty bit, Line size, Cache filling, Cache thrashing, Cache Aliasing and Burst transfer.
7) Cache-aware embedded programming: How to tackle with DMA in drivers? Code size and data size within a page to avoid cache thrashing (Linux).
8) What is self-modifying code? What needs to be taken care with self-modifying code?
9) Sample code for Cache Invalidate-all, Cache flush-all and Cache flush or invalidate a particular region.
10) Modern caches, write-buffers and troubleshooting

µITRON Specification 4.0 walkthrough

1) Differentiate on dispatch__: execute and see

Kernel systems calls are atomic.

a) CPU locked -> All interrupts, timer handlers and dispatch NOT necessarily disabled. But, does not occur..(current execution is highest precedence)
b) CPU unlocked
c) Transitional state (neither CPU locked nor CPU unlocked.. In, NORTi Transitional state = CPU locked )

The task suspend system call checks whether the dispatch has been disabled? How it handles the pending dispatch??

Delayed exeuction of service calls - Do system calls execute the dispatch when called from ISR? Or, it has distinction from executing from task contexts?

STM32F4DISCOVERY Speaker interface

howto interface speaker to STM32
http://www.arm.com/ja/support/university/students/embedded/embedded-systemsmcus-development-boards-for-students.php
http://hackaday.soup.io/tag/stm32