Cortex-M3/M4: Hardfault at SVC instruction

If you caught Hard Fault exception and the PC value stacked for the exception points to the next instruction of SVC call, then there may be problem in Base priority(BASEPRI) value or Exception Masking Register (PRIMASK) value. The causes and corresponding solutions can be cosidered as follows:

Cause 1) : SVC priority has been masked by Base Priority Mask Register (BASEPRI) :

If SVC is executed from the context which has higher priority than SVC, Hard Fault Exception will occur. An example is, SVC is executed from a Task where BASEPRI value is set lower or equal to the SVC priority value set by System Handler Priority Register 2. Another example is, SVC is executed from a interrupt service routine of higher priority interrupt than SVC.

To solve this, always initialize the SVC priority to be higher than the executing contexts.

Cause 2) : SVC has been disabled through Exception Masking Register (PRIMASK = 1) :

When PRIMASK register is set to 1, only NMI and Hard Fault Exceptions are allowed. If SVC is executed when PRIMASK is set to 1, HardFault Exception will occur.

To solve this, instead of using PRIMASK to mask interrupts, use BASEPRI to mask particular interrupts.

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