Saturday, March 24, 2012

Howto trace/debug an exception in Cortex-M3 and Cortex-M4

1) Take the current Link Register of the exception being serviced:

2) If BIT2 of the Link Register is set (for example, 0xfffffffd), take Process Stack Pointer (PSP).
If BIT2 of the Link Register is 0 (for example, 0xfffffff9), take Main Stack Pointer (MSP).

3) The PC stored at offset 24 (0x18) of the MSP or PSP refers to the address of the instruction that caused the exception or the instruction next to the instruction that caused the exception. If the PC is invalid, the LR stored at offset 20 (0x14) of the MSP or PSP refers to the instruction next to the instruction that caused the exception.

LR is 5 th register from MSP or PSP; PC is 6 th register from MSP or PSP, as follows:

4) Find the cause from that instruction.


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