It is very confusing to read the Renesas SuperH architecture user's manual in English version about MMU and memory map of SH-4A. They confuse the address translation and virtual address. They call 0x80000000 ~ 0xbfffffff as virtual address though the address translation does not happen for this address space even if you enable the MMU. I consider these are not virtual addresses but just shadow memory space or memory window which reflects other physical address space. In legacy devices, it just reflected the physical address space of just removing the MSB 3 bits, in other words, 0x80000000 ~ 0x9fffffff reflects the physical space of 0x00000000 ~ 0x1fffffff. Same way, 0xa0000000 ~ 0xbfffffff too reflected the same physical space of 0x00000000 ~ 0x1fffffff with the exception that this window is non-cacheable and the previous one is cacheable. In recent devices such as SH-4A, the physical address space is extended to the 32 bit and the window can be configured to reflect different physical address space through configuring PMB (Privileged Space Mapping Buffer). And note that the cache attributes too become configurable for these memory windows through the PMB.
SuperH architecture does not provide flat and free physical as well as virtual address space. In each it has reserved areas for the architecture specific definitions. For example, it has reserved 0x1c000000 ~ 0x1fffffff (called area7) addresses in physical address space for the architecture specific control registers. Also, it has reserved 0xfc000000 ~ 0xffffffff to shadow the same registers. Similarly, it has reserved some other areas too. We will see those areas in below sections. The virtual address space also is not flat and only some fixed address ranges are a
vailable. 0x00000000 ~ 0x7fffffff, 0xc0000000 ~ 0xdfffffff are the only the two available virtual memory address spaces. Other areas are not available for MMU translation and they just reflect some fixed memory contents over physical address space.
Legacy Physical address space:
Legacy SuperH architecture allows only less than 512 MB of physical address space with the 29 bit address bus. This address space is mostly shadowed in other regions such as P1 (0x80000000 ~ 0x9fffffff), P2 (0xa0000000 ~ 0xbfffffff) and P4 (0xfc000000 ~ 0xffffffff).
Legacy SuperH architecture allows only less than 512 MB of physical address space with the 29 bit address bus. This address space is mostly shadowed in other regions such as P1 (0x80000000 ~ 0x9fffffff), P2 (0xa0000000 ~ 0xbfffffff) and P4 (0xfc000000 ~ 0xffffffff).
Recent Physical space:
In recent devices such as SH-4A, the address bus is extended to 32 bits.
A more detailed one. You can connect devices in all over the 32 bit physical space except the SH reserved space. But, it does not mean that you can directly access your devices with the physical address it has been connected. Two areas 0x80000000 ~ 0x9fffffff and 0xa0000000 ~ 0xbfffffff needs to be mapped explicitly through PMB. See the detailed picture below:
Other short descriptions about each area:
P0, U0:
It spans in around 2GB (0x00000000 ~ 0x7fffffff) of address space. When MMU is enabled, it becomes the largest virtual address space. The underlying the Physical addresses on this area are shadowed in different areas. So, this virtual address space can be mapped one to one with physical address space or in other way.
P1, P2:
These are memory windows for the privileged mode to access different physical address spaces.
These addresses are not translated through TLB. But, the different physical address spaces can be mapped through PMB in recent devices. In legacy device, just reflect the physical corresponding to the 3 MSBs with 0 value.
P3:
This is the only address space where virtual mapping also can be done as well as the connected devices can be accessed directly with the same physical addresses as they are mapped.
P4:
This will have different view on User mode and Privileged mode. In user mode, it give access to On chip RAM (cache) and store queues. But, in privileged mode, it gives access to TLBs, PMB, Control registers, etc. But, this area is completely reserved for the architecture.
Overall interesting picture from ARM:
In recent devices such as SH-4A, the address bus is extended to 32 bits.
A more detailed one. You can connect devices in all over the 32 bit physical space except the SH reserved space. But, it does not mean that you can directly access your devices with the physical address it has been connected. Two areas 0x80000000 ~ 0x9fffffff and 0xa0000000 ~ 0xbfffffff needs to be mapped explicitly through PMB. See the detailed picture below:
P0, U0:
It spans in around 2GB (0x00000000 ~ 0x7fffffff) of address space. When MMU is enabled, it becomes the largest virtual address space. The underlying the Physical addresses on this area are shadowed in different areas. So, this virtual address space can be mapped one to one with physical address space or in other way.
P1, P2:
These are memory windows for the privileged mode to access different physical address spaces.
These addresses are not translated through TLB. But, the different physical address spaces can be mapped through PMB in recent devices. In legacy device, just reflect the physical corresponding to the 3 MSBs with 0 value.
P3:
This is the only address space where virtual mapping also can be done as well as the connected devices can be accessed directly with the same physical addresses as they are mapped.
P4:
This will have different view on User mode and Privileged mode. In user mode, it give access to On chip RAM (cache) and store queues. But, in privileged mode, it gives access to TLBs, PMB, Control registers, etc. But, this area is completely reserved for the architecture.
Overall interesting picture from ARM:
2 comments:
This is SUPER helpful, thanks. What still confuses me is the use of the upper 3 bits even though they aren't utilized. For instance, the reset vector on a SH-3 is 0xA0000000, how is that different from 0x80000000? I do understand there are some on-chip registers mapped into some of these memory blocks so is that the reason for it?
I'm disassembling some old firmware and seeing 0xAxxxxxxx and 0x8xxxxxxx used almost interchangeably is super confusing.
If you access the memory using 0x8xxxxxxx it will be accessed through the Cache. That mean, the memory contents are transferred to Cache and CPU reads from Cache. It is good to access program and data through this space, because it will increase the execution speed by reducing the memory access time. (CPU -> Cache -> 0x8xxxxxxx)
If you access the same memory using 0xAxxxxxxx address space, the CPU will read directly from the Physical device, not through the Cache. I/O devices and Memory buffers used in DMA are needs to be accessed through this address window. (CPU -> 0xAxxxxxxx)
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