Write Buffers:
Do you know NCM? It is just accumulating the data and sending instead of sending each packet separately to improve the overall throughput. But it does not meant that the transfer would be postponed forever till accumulating the enough data. It will happen at next earliest possible timing. (Not like caches which will postpone the write till eviction) Instead of I/O device, it will write on write buffer and write buffer will do it soon. It is similar to a server thread passing the requests to a set of worker threads. For example, the CPU or Cache boss needs to post a letter. He puts the request to James, "Hey James! Just post this letter. I need to do a telephone call". James just went out taking the letter. He may be on the way to the post office. But, Boss is not sure when James will complete the post. Just to make sure, he may say "Hey James! Just post this letter and bring me a class of water!". So, the next task can be a dummy read or some valid transaction. But, to make sure that James does all the tasks in orderly fashion, the memory type needs to be set as "Device".
https://www.google.co.jp/#q=Write+buffer+dummy+read
"Strongly ordered" memory type is CPU boss himself is doing all the stuff in orderly fashion.
Store Queues:
Store Queues are considered as one-way (write only) Cache which can do burst write access with memory.
An LCD display system will be used as an example. The CPU draws the picture, the LCD controller displays it.When the underlying content is changed completely, the entire display data must be overwritten. When the cache is being used in the write back mode, previous data is copied to the cache entry because of the cache miss access. The data that was read into the cache is overwritten without being used, so this read operation is wasted. If the store queue is used, there is no read access such as cache fill accesses, only write accesses. 32 bytes size data are written at a time when the data are written back into memory from SQ. For example, with synchronous DRAM, this access becomes a burst access, making a high speed write back access possible. The prefetch (PREF) instruction is used to write back to memory.
Do you know NCM? It is just accumulating the data and sending instead of sending each packet separately to improve the overall throughput. But it does not meant that the transfer would be postponed forever till accumulating the enough data. It will happen at next earliest possible timing. (Not like caches which will postpone the write till eviction) Instead of I/O device, it will write on write buffer and write buffer will do it soon. It is similar to a server thread passing the requests to a set of worker threads. For example, the CPU or Cache boss needs to post a letter. He puts the request to James, "Hey James! Just post this letter. I need to do a telephone call". James just went out taking the letter. He may be on the way to the post office. But, Boss is not sure when James will complete the post. Just to make sure, he may say "Hey James! Just post this letter and bring me a class of water!". So, the next task can be a dummy read or some valid transaction. But, to make sure that James does all the tasks in orderly fashion, the memory type needs to be set as "Device".
https://www.google.co.jp/#q=Write+buffer+dummy+read
"Strongly ordered" memory type is CPU boss himself is doing all the stuff in orderly fashion.
Store Queues:
Store Queues are considered as one-way (write only) Cache which can do burst write access with memory.
An LCD display system will be used as an example. The CPU draws the picture, the LCD controller displays it.When the underlying content is changed completely, the entire display data must be overwritten. When the cache is being used in the write back mode, previous data is copied to the cache entry because of the cache miss access. The data that was read into the cache is overwritten without being used, so this read operation is wasted. If the store queue is used, there is no read access such as cache fill accesses, only write accesses. 32 bytes size data are written at a time when the data are written back into memory from SQ. For example, with synchronous DRAM, this access becomes a burst access, making a high speed write back access possible. The prefetch (PREF) instruction is used to write back to memory.
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